1. Field of the Invention
The present invention relates to MOS type semiconductor devices in which a plurality of MOS structures are formed on one surface of a semiconductor substrate so that the current flowing between main electrodes are controlled by the channel current of respective MOS structures.
2. Discussion of the Related Art
Typical of such MOS type semiconductor devices are the vertical power MOS-FET and the insulated gate type bipolar transistor (IGBT). FIG. 7 shows the structure of a conventional vertical power MOS-FET in which a high resistance n.sup.- drain region 1 is formed over an n.sup.+ drain contact layer 2. A plurality of p.sup.- channel diffusion regions 3 are formed on the surface of the high resistance drain region 1 with corresponding low resistance p.sup.+ well diffusion regions 4 in the middle thereof. On the surface of the respective channel diffusion regions 3 is formed a pair of n.sup.+ source regions 5. Each pair of n source regions 5 is separated by a predetermined distance. A gate electrode 7 of polysilicon crystal, for example, is formed on gate oxide layer 61 so that an n-channel is formed on the surface layer 31 of the drain of the channel diffusion region 3 between separated source regions 5. A source electrode 8 is formed in contact with p.sup.+ well region 4 and the source regions 5 via the gate electrode 7 and insulation layer 62 which is typically made of PSG. A drain electrode 9 is in contact with the drain contact layer 2. In an IGBT structure, a P layer is formed instead of, or under, the n.sup.+ layer 2.
Each of these MOS type semiconductor devices includes a parasitic pnp bipolar transistor constructed of the n.sup.+ source region 5, p.sup.- channel region 3, and n drain region 1. When an avalanche current flows into a pn junction between the p.sup.- channel region 3 and n.sup.- drain region 1 due to a reverse voltage impressed during a transient period, the above-mentioned parasitic transistor goes active and may cause damage to the MOS semiconductor device.
In order to avoid such damage, various methods of preventing the parasitic bipolar transistor from going active are used. These methods include increasing the diffusion depth of the p.sup.- well region 4 to help avalanche occur across a pn junction formed between p.sup.+ well region 4 and n.sup.- drain region 1. As a result, avalanche current through this pn junction is increased. However, the avalanche current through the p.sup.- channel region 3 as a base region of the parasitic bipolar transistor is correspondingly decreased. Improvement of avalanche-sustaining margin by deep diffusion of the p.sup.- well region 4 suffers from the problems that the sustaining voltage decreases and the ON resistance increases. Another method of inhibiting the parasitic bipolar transistor decreases the resistance of the p.sup.- channel region 3. However, any method of inhibiting the parasitic bipolar transistor is susceptible to limitations in the process used to construct the semiconductor device. The same is true for the IGBT and p channel MOS type semiconductor devices in which the conductivity types are reversed from those discussed above.